A method of switching a switching element when the input voltage thereof is substantially zero so as to lower the loss of a switching power supply circuit is disclosed in patent document 1. FIG. 10 is a circuit diagram of a switching power supply circuit 901 corresponding to the circuit disclosed in patent document 1. The power supply circuit 901 converts a direct-current voltage Vin from a power input portion 902 into another direct-current voltage Vo and outputs it (Vin<Vo).
In the power supply circuit 901 of FIG. 10, during the period in which a switching element Q1 is on, energy is stored in an inductor L2, and during the period in which the switching element Q1 is off, a capacitor C1 is charged and is thereafter changed into a discharged state. During this discharge period, a switching element Q2 is turned off to discharge charge stored in the parasitic capacitance of the switching element Q1, and with a voltage across both ends of the switching element being substantially zero, the switching element is turned on (this is referred to as zero voltage switching). It is assumed that in the power supply circuit 901, the charging voltage of the capacitor C1 is maintained at a constant value Vc. The side of the switching element Q1 is the positive terminal of the capacitor C1.
FIG. 11 is an operation timing chart of the power supply circuit 901 in FIG. 10. In FIG. 11, the vertical axis corresponds to a voltage or a current, and the horizontal axis corresponds to time. In FIG. 11, waveforms 911 to 919 are respectively the voltage waveform of a gate signal Q1g of the switching element Q1, the voltage waveform of a gate signal Q2g of the switching element Q2, the waveform of a current L1i flowing through an inductor L1, the waveform of a current L2i flowing through the inductor L2, the waveform of a current Q1i flowing through the switching element Q1, the waveform of a current Q2i flowing through the switching element Q2, the waveform of a current D1i flowing through a diode D1, the waveform of a drain-source voltage Q1v of the switching element Q1 and the waveform of a drain-source voltage Q2v of the switching element Q2. In the currents Q1i and Q2i, the polarity of the current flowing from the drain to the source is assumed to be positive.
First, during the period (period before a time T0 in FIG. 11) in which the gate signal Q1g is turned high, and the switching element Q1 is on, in a path passing through the positive terminal of the power input portion 902, the inductor L1, the inductor L2, the switching element Q1 and the negative terminal of the power input portion 902, the current Q1i of the switching element Q1, the current L1i of the inductor L1 and the current L2i of the inductor L2 flow, with the result that the currents Q1i, L1i and L2i are linearly increased (at a gradient of Vin/(L1+L2)). During the period in which the switching element Q1 is on, the switching element Q2 is off, and consequently, the current Q2i is zero. The values of the currents L1i, L2i and Q1i at the time T0 are represented by Ip (Ip>0).
When at the time T0, the switching element Q1 is turned off, the current Q1i of the switching element Q1 is decreased from Ip to zero, and the drain-source voltage Q1v of the switching element Q1 is increased, with the result that the current Q2i starts to flow from the source to the drain of the switching element Q2 and thus the drain-source voltage Q2v of the switching element Q2 is decreased. The initial value of the current Q2i that starts to flow when at the time T0, the switching element Q1 is turned off is (−Ip).
When at a time T1, the voltage Q1v reaches a voltage “Vo+Vc”, a current flows both through a path passing through the positive terminal of the power input portion 902, the inductor L1, the diode D1, a capacitor Co and the negative terminal of the power input portion 902 and through a path passing through the inductor L1, the inductor L2, the parasitic diode of the switching element Q2, the capacitor C1 and the capacitor Co, with the result that the current L1i is linearly decreased (at a gradient of (Vo−Vin)/L1), the current L2i is linearly decreased (at a gradient of −Vc/L2), the current Q2i is linearly increased (at a gradient of Vc/L2), the current D1i (=L1i−L2i) is linearly increased and the current Q2i becomes zero at a time T2. A control circuit 910 turns on the switching element Q2 during the period between the time T1 and the time T2, that is, during the period in which the negative current Q2i flows through the switching element Q2, and thereby realizes the zero voltage switching of the switching element Q2.
At and after the time T0, the current Q2i that has been increased from (−Ip) at the gradient of “Vc/L2” continues to be increased at the same gradient of “Vc/L2” even after the current Q2i becomes zero at the time T2. At a time T3, the gate signal Q2g is turned low, and thus a resonant operation is started between the inductor L2, the output capacitance of the switching element Q1 and the output capacitance of the switching element Q2, the voltage Q2v is increased while the voltage Q1v is decreased and the voltage Q1v becomes zero at a time T4. This resonant operation causes the parasitic diode of the switching element Q1 to become conductive and the negative current Q1i flows at and after the time T3 until a time T5, which will be described later. Since when the charging voltage Vc of the capacitor C1 is constant, “(charging current of the capacitor C1)=(discharge current of the capacitor C1)” holds true, at the time t3, L2i=−Ip and Q2i=Ip.
During the period (that is, during the period between the time T4 and the time T5) in which the negative current Q1i flows through the switching element Q1 after the voltage Q1v becomes zero at the time T4, the control circuit 910 turns the gate signal Q1g high, and thereby realizes the zero voltage switching of the switching element Q1. At and after the time T3, the currents Q1i and L2i are linearly increased (at the gradient of Vo/L2), the current D1i is linearly decreased and at a time T6, D1i=0 and L1i=L2i=Q1i. 
Patent document 2 discloses a configuration that is designed for improving the circuit configuration in patent document 1.